Chip Designer - Center for Cyber Security (Fixed Term for 2 Years)

Posting Number 2022-10458
Posted Date 1 month ago(7/7/2022 2:43 PM)
Center for Cyber Security (CCS-AD)
NYU Abu Dhabi (AD00001)
Is relocation available for this job?

Position Summary

UAE Nationals are encouraged to apply

New York University Abu Dhabi (NYUAD) seeks to appoint a Chip designer reporting to Professor of Electrical and Computer Engineering; Global Network Professor of Electrical and Computer Engineering, Tandon School of Engineering, NYU.


We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip (SoC) targeted to prototype the cutting-edge research works in the field of hardware security.


Key Responsibilities:

  • Develop and own physical design implementation of low-power and high-performance designs, including floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes
  • Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution
  • Work with the Researchers and RTL design team to understand design architecture and drive physical aspects early in the design cycle and work with them to drive design modifications to resolve congestion/timing issues and implement functional ECOs
  • Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality
  • Interact with the tapeout service company to understand all the deliverables and timelines


Required Education:

  • Bachelor's degree in Computer Science, Computer Engineering, Electronics Engineering relevant technical field, or equivalent practical experience
  • Programming/scripting skills: TCL, Python, Perl, or Shell

Required Experience:

  • Experience in physical design and timing closure
  • Knowledge of RTL2GDSII flow and design tape-outs in 22nm or below process technologies
  • Experience with EDA tools like Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre
  • Hands-on experience in floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs
  • Knowledge of geometry/process/device technology implications on physical design
  • Experience with large SOC designs (>20M gates) with frequencies over 1GHZ
  • Interpersonal, teamwork, and communication skills and experience interfacing with cross-functional teams, IP, and EDA vendors



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